AREA EFFICIENT AND HIGH-SPEED SIGNIFICANT CARRY SELECT ADDER BY USING EFA, FTFA 1, AND FTFA 2.

CHAPTER 4

DESIGN AN AREA EFFICIENT AND HIGH-SPEED SIGNIFICANT CARRY SELECT ADDER BY USING EFA, FTFA 1, AND FTFA 2.

4.1 INTRODUCTION

The conventional multiply and accumulate unit have the sum of the previous consecutive product. The multiplication is considered as the fundamental function that can be applied to the purpose of the digital signal processing.  They require the many hardware-based resources, and they also process at the duration when compared to the subtraction and addition. The typical processing of the Multiplier. That can help to compute. The computer is considered as the central processing unit that can be devoted due to the consideration of the amount of the processing time of implementing the arithmetic function, particularly in the service of multiplication. When the high performance based on the digital signal processing based system that can be relied upon to the hardware-based repetition to attain the significant data-based throughput. Here consider the function of the Multiplier is the vital component for the contribution of total power consumption substantially in the system. The multiply and accumulate unit is represented as the MAC unit that contributes to the essential function. So it can need high speed based Multiplier. In the present, multiplication based time can be considered as the dominant factor for founding the instruction based cycle time consideration on the digital signal processing based chip. The amount of circuitry involved is directly proportional to the square of its resolution. In the past, many novel ideas for multipliers have been proposed to achieve high performance. The demand for high-speed processing has been increasing as a result of expanding computer and signal processing applications. More top throughput arithmetic operations are essential to achieve the desired performance in much real-time signal and image processing applications. One of the critical arithmetic operations in such applications is multiplication, and the development of a fast multiplier circuit has been a subject of interest over decades. Reducing the time delay and power consumption is essential for many applications.

The main aim of the digital signal processing based process design id helps to enhance the speed. The improved speed based on the MAC unit. When the high-speed energy-based arithmetic logical unit design with the help of the Vedic function. The implementation of the arithmetic logical unit with the purpose of subtractor, adder, Vedic Multiplier, as well as the MAC unit. The Vedic Multiplier can be implemented in the MAC unit. The Vedic Multiplier based architecture helps to determine the rapid improvement over the conventional shift and the algorithm. When they compare to the implementation of the Vedic Multiplier with the standard Multiplier, they will claim the similar number of multiplication as well as addition based function that can be required in the Vedic Multiplier as well as the standard Multiplier, when they test and also compare the implementation based on the Multiplier included as multiplier macro, array multiplier and Vedic Multiplier with the full portioning, when the Vedic Multiplier can have the purpose of four-bit macro, entirely based recursive Vedic Multiplier. The Vedic Multiplier with the propose of the 8 bit macro for the implement the very high optimized speed

The Multiplier can be implemented in many algorithms, the multiplier architecture, which is similar to the array multiplier. In any multiplier can be separated into three categories. When the partial production generation category, partial products addition category, as well as the final addition category. When the first category, the Multiplier and the multiplicand with the multiplied bit by bit for generating the partial products to the half. In the second category, it helps to minimize the amount of the partial product to half. The second category is the most important, as it is the most complicated and determines the speed of the overall Multiplier. In the last stage, the two-row outputs of the tree are added using any high-speed adder such as a look-ahead adder to generate the output result. The Multiplier can be categorized for the relatives for their application based on the architecture, and they have some way the partially based product. When the partly based product that can be produced and they also summed up. They are array multiplier as well as tree multiplier. In the array multiplier, the counter, as well as compressors, are connected in a series fashion to all bit slices of the partial product parallelogram.

They perform an M bit by N bit multiplication. When the M bit multiplicand A=a(M-1)a(M-1)……..a1a0 is to be multiplied by the N bit multiplier B=b(N-1)b(N-2)c(N-3)….p1p0. The unsigned binary number. The generic multiplier block diagram is shown in figure 4.1.

M bit multiplicand

N bit multiplier

Figure 4.1 generic block diagram of a multiplier

The multiply and accumulate unit that can compute d the multiply of the two numbers and then adds that multiply to an accumulator. The multiply and collect group, which consists of the Multiplier, followed by the adder as well as an accumulator. They register, and it can be stored the output when they clocked. The result of the register can be fed back to one input. The input of the adder. So that on each clock when the multiplier output is added to the record. When the combinational Multiplier can require a large amount based logic. They also compute a product much more fast when compare with the process based on the shifting as well as adding that can be typical of the earlier computers. The multiply and accumulate unit circuit is attained to the overflow. They might happen for the amount of multiply and collect unit based function. The function of the MAC unit is significant. The flood is considered in the signed adder that can occur from the two operands with a similar sign can contribute the result when the different sign.

The proposed MAC unit architecture. The Vedic Multiplier should increase the multiply and accumulate unit can be designed with high speed. When the carry-save adder is attained in an accumulator in this design. The Vedic Multiplier and carry-save adder in the multiply and accumulate unit. The design can be enhanced from the MAC unit that can be modified from the high speed. That can be contributing to the better gain performance of the system. When the product of the two numbers. They can be fed back into the 32 or 16-bit carry-save adder. A similar product can be contributed again to the next product of the two numbers.  When the multiply and accumulate unit that can be capable of adding as well as multiplying with the past product consequently. When they contribute the three or more operand. That operand can be added simultaneously for the two operand adder,  the time consuming of the carry propagation can be repeated in the more times. If the number of operands is to be considered. Then they carry have to propagate time. They can be represented as the (n-1) times. When the carry-save adder based addition, the propagate the carry adder can be multiplied. Another stage should be considered as the partial sum and sequence of the carries. They can be generated separately. The module of the register of the multiply and accumulate unit that can be implemented with the help of bit register. The out 32 bit from the accumulator becomes the input to bit register. They produce the 32 bit based output. The architecture of the MAC unit is shown in figure 4.2.

Multiplicand                                     Multiplier

Figure 4.2 Architecture of MAC unit

The concept of the carry select adder is to compute the alternative based results in the parallel, and they can be after to select the correct result for the single as well as multiple output based stages in the hierarchical based techniques. To enhance them in performance based on speed, the select carry order can be increased for the area requirement. In the carry, a select adder for both the sum as well as carry bit can be used to calculate the two alternatives. When two o options are considered as input, carry “0” and “1”. Once the carry-in is delivered. The correct computation has been chosen for MUX. They produce them the desired output.  Therefore instead of waiting for them for the carry input, they have to be calculating the sum. The sum is correct output as soon as they carry-in. The time taken to compute the amount is  18 then avoided, which results in a good improvement in speed.

4.2 MULTIPLIER DESIGN

The following section presents the design of the multiplier topology. In this work, the following multiplier structures are synthesized and analyzed for the proposed MAC unit.

Array multiplier

Dadda multiplier

Wallace multiplier

Vedic Multiplier

4.2.1 ARRAY MULTIPLIER

When the conventionally based array multiplier can have the purpose of the carry-save adder that can add the product, thus the carry-save addition based method, hence the first row that can be either the half adder as well as full adders. When the first row in a partial product that can be implemented at the full adder.

As the carries at each of the full adders that can be diagonally forward to the row in the snake. The resulting based Multiplier can be considered as the carry-save array multiplier. As the carry bit cannot be immediately added. So they can be instead saved at the stages when the array-based Multiplier can be considered as the efficient layout in the combinational Multiplier.  Due to the multiplication of the two binary number that is attained at the one micro-based function for the circuit, it can be a form of product-based bit entire at the once that they make as the express condition for the multiply the two numbers with the only delay at the time of the signal for they propagate through the gates they can form the multiplication based array. Then the array multiplier can have created the collection based multiplication. When the array multiplier has a regular structure, then the layout can be simple, they also occupy the less area. They also have a small size. The multiplication based method in which the array of the cells which can be identical generates new partial based product as well as accumulation of it at the same time.

Figure 4.3 Array multiplier

4.2.2 DADDA MULTIPLIER

When the Dadda multiplier can be considered as the hardware multiplier based design, the can be introduced from a computer-based scientist name was Luigi Dadda in the year 1965. The Dadda multiplier process can be similar to the Wallace multiplier. It can be faster slightly when compared to Wallace multiplier. In the reason of all the size of the operands as well as they will require the fewer gates, they also depend upon the entire, but it can be small based operand sizes.

In both multipliers can have three possible steps with the two-bit strings as well as length simultaneously.

1. The logical and gate based Multiplier considers each bit as well as by each bit that can yield the output, as well as the group with the help of weight, which occurs in the columns.
2. The number of the product based on partial stages can be minimized when the steps depend on the full adder as well as half adder due to each weight of the most critical two bits.
3. Now they add the entire output with the conventional adder.

When the Wallace multiplier, the product of the multiplication can be considered as the being stage of the weight-based various kind of carry that can reflect the magnitude that can be obtained at the original bit ranges in the multiplication.

Unlike the Wallace based multipliers can be considered as minimized as much as possible in each based layer. When the Dadda based Multiplier can attain the minimum cost expenditure based on the phase reduction stage are shown in figure 4.4. They can be requiring the full amount with the fewer bits that can be longer as well as they can be a slightly bigger adder.

Figure 4.4 Dadda multiplier

4.2.3 WALLACE MULTIPLIER

            The multiplication can be considered as one of the important as well as widely used for arithmetic function. When the full value based on multiplier architectures that can be reported with providing flexible choices for various purposes. When it is similar to array multiplier. They also present better performance when compare with another multiplier. The Wallace based Multiplier uses both full adders as well as half adders that can be minimized from the partial product tree to two rows, and then a final snake is used to add these two rows of partial products. It is also considered as the traditional Wallace based Multiplier. They even perform the function that can also follow some steps.

• To generate the entire product based on partial.
• When product tree based on partial can be minimized, it the help of full adders and half adders until it is reduced to two terms.
• The fast adder can be used to add the two terms.

When the based on the multipliers depends on the Wallace reduction based tree that requires an efficient-area based strategy with high multiplication speed. When the amount of modification can be presented for they optimized an area of the Wallace based Multiplier. The Wallace based Multiplier can also reduce space cannot compromise on the speed based original Wallace multiplier. The Wallace multiplier can be lowest based on the compared to anther tree-based compared Multiplier.

8-bit Multiplicand 8-bit Multiplier

16 Product

Figure 4.5 Wallace multiplier

This advantage becomes more pronounced for multipliers bigger than 16 bits. In traditional Wallace architecture, all the bits of all of the partial products in each column are added together by a set of counters in parallel without propagating any carries. Another set of shelves then reduces this new matrix and so on, until a two-row form is generated. Wallace method uses three-steps to process the multiplication operation.

• Formation of bit products.
• The bit product matrix is reduced to a 2-row form by using a carry-save adder.
• The remaining two rows are summed using a fast carry propagate adder to produce the product.

MERITS

The propagation delay in this Multiplier is reduced in comparison to the array multiplier.

DEMERITS

Wallace multiplier has a limitation of being very irregular, so an efficient layout is not possible.

Routing between the levels becomes complicated, and longer wires have higher capacitance.

4.2.4 VEDIC MULTIPLIER

            Multiplication-based on the operation such as well as multiply and accumulate, and inner product can be among them some of the frequently used Computation-Intensive Arithmetic Functions currently implemented in many Digital Signal Processing applications. The Vedic Multiplier has been great importance of the data path computation. When the efficient Vedic multiplier architecture supersedes booth’s Multiplier, a renowned multiplication algorithm. Therefore, if you can design a suitable architecture for the Vedic Multiplier, it will be an excellent help for signal processing involving multiplication computation. They can be many Digital Signal Processing applications such as convolution, based on the Fast Fourier Transform, filtering, and microprocessors m it’s arithmetic and logic unit. When the multiplication dominates the execution tune of most Digital Signal Processing algorithms, so there is a need for high-speed Multiplier. They currently multiplication time is still the dominant factor in determining the instruction cycle time of a Digital Signal Processing chip. When the demand based on the very high speed based processing has been increasing as a result of expanding computer and signal processing applications. More top throughput arithmetic operations are essential to achieve the desired performance in many real-time signal and image processing applications. One of the critical arithmetic operations in such applications is multiplication, and the development of a fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the quick and low power multipliers. Employing this technique in the computation algorithms will reduce the complexity, execution time, power, etc. This Vedic based Multiplier is compared with binary Multiplier based on the partial products method. The speed comparison of the 16*16 Vedic based Multiplier is shown in the below figure 4.6.

Figure 4.6 16*16 Vedic multiplier

4.3 PROBLEM STATEMENT

The fundamental function of the more important for the digital system. When the fastest, as well as more reliable, service, occur in the digital-based order. They can be performed with some resident adder that they rely on the purpose of the single cells, and they also possess a regular connection among them. The significant issues based on the multiple based bit addition functions occur in the carry propagation delay. When the entire adder can be presented, carry select snake that can require a better compromise among the speed based performance area efficiency as well as cost expenditure. When the comparison of the entire three designs based on the state of the art adder such as carry select adder, exact full adder with the reference its error matrices, area, delay, as well as power-based performance. The inefficient area, speed, propagation delay, and the utilization of significant error tolerance are incapable of managing the networks in an Image and signaling processing based adder cells. The problem overcome with the presented carry select adder, exact carry choose viper, fault-tolerant design1, fault-tolerant design 2. The multiplier design based on the array, data, Wallace as well as Vedic. When the comparisons based on Vedic multiplication or Vedic mathematics. The presented systems that can require conventional accuracy. They also optimized the efficiency of the area along with the digital-based processing of the error based tolerant adder. They enumerate the improve the speed efficiency between the entire viper based function.

4.4 PROPOSED METHODOLOGY

4.4.1 CONVENTIONAL FULL ADDER

The conventional full adder has to be implemented at the numerous various kinds of ways, including as they can be a custom based level of transistor circuit as well as compose another gate. When A and B can be represented as the inputs. When Cin can be considering the carry based input can be expressed for the SUM and can be considered as the following.

SUM = A. B. Cin+ A. B. Cin +A. B. Cin +A. B. Cin

SUM= Cin (A.B+A.B) + Cin (A.B+A.B)

= A (XOR) B (XOR) Cin

CARRY= A. B + A. Cin + B. Cin

CARRY= A.B + Cin (A+ B)

It can be implemented with the purpose of the three inputs based XOR gates, two AND gates with one OR gate. When the level of the transistor can be implemented with the help of several transistors (42 transistors).

Figure 4.7 Conventional full adders

4.4.2 PROPOSED EXACT FULL ADDER

The presented design function can be attained in the exact full adder. When they contain the more accurate as well as better significance. There is an approximation based factor of snake that can be implemented with the exact full adder based cell. The logic expression can be considered as SUM and CARRY based outputs of the exact full adder are shown respectively. The gate-level based implementations of the exact full adder are shown in figure 4.8.

SUM =A^ B ^ Cin

CARRY= A. B+ B. Cin +A.Cin

A   A                            B      A                                      B    A             B     A

CARRY        SUM                                      SUM                            SUM               SUM

Figure 4.8 Proposed EFA block diagram

The implementation of the proposed exact full adder using cadence tools. When the exact full adder using the various kinds of the adder and 8*8 Vedic Multiplier has to be designed, they can be implemented as well as analyzed among their performance-based parameter are shown in figure 4.11.

4.10 proposed EFA design

4.4.3 PROPOSED FAULT TOLERANT FULL ADDER

Table 1 denotes the logic expression of the SUM and CARRY based output of the proposed fault-tolerant full adder that can be determined. When the gate level of fault-tolerant full adder designs can be shown in figure 4.9, 4.10.

SUM= A^ (B+ Cin)

CARRY= A+ (B. Cin)

In the presented the FTFA design, the fault-tolerant full adder based cell can be introduced with the error in the SUM as well As the error in the CARRY.

SUM= (A^B)*(~ Cin)

CARRY= Cin

Figure 4.9 FAFT design 1

Figure 4.10 FAFT design 2

Table 1The logic expression of the proposed design

The presented fault-tolerant full adder based cell design is shown in below figure 4.12. When the final design by using the exact full adder, that can be considered as the appropriate adder. The present fault-tolerant full adder can help to optimize the implementation. They also give the most efficient area as well as accuracy design. There are two various kinds of FTFA design. One is FAFT design 1, and another one is FTFA design 2.  The proposed fault-tolerant design based cell can be introduced to the error in the SUM as well as failure in the CARRY.

Figure 4.12 a Proposed FTFA design 1

Figure 4.12 b Proposed FTFA designs 2

Figure 4.12 proposed FTFA design

DESIGN UTILIZATION

The consistent utilization of exact full adder, fault-tolerant full adder design one, and fault-tolerant full adder design two are shown in table 2.

Table 2 the logic utilization of proposed design

4.5 PROPOSED MULTIPLIER DESIGN

4.5.1 PROPOSED ARRAY MULTIPLIER DESIGN

The overall RTL based array multiplier is shown in figure 4.13 a. The schematic diagram of the array multiplier that can be used shown in figure 4.13 b.

Figure 4.13a overall RTL array multiplier

Figure 4.13b schematic array multiplier design

4.5.2 PROPOSED DADDA MULTIPLIER DESIGN

The overall RTL based Dadda multiplier is shown in figure 4.14 a. The schematic diagram of the data multiplier that can be used is shown in figure 4.14 b.

Figure 4.14a overall RTL data multiplier

Figure 4.14b schematic data multiplier design

4.5.3 PROPOSED VEDIC MULTIPLIER DESIGN

The overall RTL based Vedic Multiplier is shown in figure 4.15 a. The schematic diagram of the Vedic Multiplier can be used, as shown in figure 4.15 b.

Figure 4.15a overall RTL Vedic multiplier

Figure 4.15b schematic Vedic multiplier design

4.5.4 PROPOSED WALLACE MULTIPLIER DESIGN

The overall RTL based Wallace multiplier is shown in figure 4.16 a. The schematic diagram of Wallace multiplier can be used, as shown in figure 4.16 b.

Figure 4.16a overall RTL Wallace multiplier

Figure 4.16b schematic Wallace multiplier design

DESIGN UTILIZATION

The consistent utilization of various types of multiplier design is shown in table 3.

Table 3 the logic utilization of proposed multipliers design

4.6 RESULTS AND DISCUSSION

The simulation result of a proposed exact full adder by using 95.833 ns when pr [31.0], as [15.0], bs [15.0] are shown in figure 4.17a.

Figure 4.17a schematic sequential circuit of proposed exact full adder

The simulation result of a proposed exact full adder by using 139.482 ns when pr [31.0], as [15.0], bs [15.0] are shown in figure 4.17b.

Figure 4.17 b schematic sequential circuit of proposed exact full adder

The simulation result of the proposed Fault-tolerant full adder design one by using 90.130 ns when pr [31.0], as [15.0], bs [15.0] are shown in figure 4.18a.

Figure 4.18a schematic sequential circuit of proposed FTFA design 1

The simulation result of the proposed Fault-tolerant full adder design one by using 140.145 ns when pr [31.0], as [15.0], bs [15.0] are shown in figure 4.18b.

Figure 4.18b schematic sequential circuit of proposed FTFA design 1

The simulation result of proposed Fault-tolerant full adder design two by using 90.995 ns when pr [31.0], as [15.0], bs [15.0] are shown in figure 4.19a.

Figure 4.19a schematic sequential circuit of proposed FTFA design 2

The simulation result of proposed Fault-tolerant full adder design two by using 139.208 ns when pr [31.0], as [15.0], bs [15.0] are shown in figure 4.19b.

Figure 4.19b schematic sequential circuit of proposed FTFA design 2

The simulation result of the proposed array multiplier by using 99.728 ns when z [31.0], x [15.0], y [15.0] are shown in figure 4.20a.

Figure 4.20a schematic sequential circuit of proposed array multiplier

The simulation result of the proposed array multiplier by using 138.993 ns when z [31.0], x [15.0], y [15.0] are shown in figure 4.20b.

Figure 4.20b schematic sequential circuit of proposed array multiplier

The simulation result of the submitted data multiplier by using 100.050 ns when z [31.0], x [15.0], y [15.0] are shown in figure 4.21a.

Figure 4.21a schematic sequential circuit of proposed dadda multiplier

The simulation result of the submitted data multiplier by using 139.830 ns when z [31.0], x [15.0], y [15.0] are shown in figure 4.21b.

Figure 4.21b schematic sequential circuit of proposed dadda multiplier

The simulation result of the proposed Vedic Multiplier by using 89.763 ns when z [31.0], x [15.0], y [15.0] are shown in figure 4.22a.

Figure 4.22a schematic sequential circuit of proposed Vedic Multiplier

The simulation result of the proposed Vedic Multiplier by using 139.068 ns when z [31.0], x [15.0], y [15.0] are shown in figure 4.22b.

Figure 4.22b schematic sequential circuit of proposed Vedic Multiplier

The simulation result of the proposed Wallace multiplier by using 89.915 ns when z [31.0], x [15.0], y [15.0] are shown in figure 4.23a.

Figure 4.23a schematic sequential circuit of proposed Wallace multiplier

The simulation result of the proposed Wallace multiplier by using 139.604 ns when z [31.0], x [15.0], y [15.0] are shown in figure 4.23b.

Figure 4.23b schematic sequential circuit of proposed Wallace multiplier

4.7 CONCLUSION

This paper presented an area-efficient using adder and carry select adder based algorithm with a better approximation for the error-tolerant based application. They also implement the presented algorithm with n-16. They reveal that the proposed fault-tolerant full adder design one and fault-tolerant full adder design two can be applied; moreover, they perform better area efficiency. Another proposed design exact full adder produces better accuracy. It is similar in both proposed FTFA 1 as well as FTFA 2.