A COMPACT AND EFFICIENT IMPLEMENTATION OF MODIFIED MMF2 ENCRYPTION AND MODIFIED DES ALGORITHM ON FPGA

A COMPACT AND EFFICIENT IMPLEMENTATION OF MODIFIED MMF2 ENCRYPTION AND MODIFIED DES ALGORITHM ON FPGA

ABSTRACT

The design of modern architectures with decreased ability is an essential challenge that electronics and PC engineers face. In this paper, we proposed contemporary architecture for the algorithm of a block cipher. To select the algorithm, MMF2 encryption is essential to decreased ability storage and hardware ability. The purpose of the algorithm contributes and internal block size of about number of bits (64 bits), with a primary key with Nine repetitions including 128 bits. The major challenge of the real work for the application of wireless networks which contain 4*4 S boxes, the S boxes are not good at security level when compare to 8*8 boxes. Here we use 4*4 S boxes should be structured by this proposed algorithm due to secure regarding differential as well as direct attack’s purpose and it should be protected. The proposed design aspires for reducing the number of blocks which is repeated. The logic locking should be convenient for hopeful, proactive security strategy beyond the high brow of belongings piracy, IP, counterfeiting, hardware Trojans, reverse engineering, and other overbuilding attacks. These attacks can be used for running chip considered as an oracle is to be released for the best launched and great retrieve its secret key. Xilinx software tools are selected in the proposed methodology and also realize the compact and efficient implementation.

Keywords: Modified MMF2, Modified DES, Hardware Trojans, Counterfeiting, Wireless network, Encryption

INTRODUCTION

The knowledge of encryption explains and determines the information that can be stored. It also operated by the on the switch operation and it also encrypted by the algorithm that can be well-known propose of the technologies it can be contributed by the forward stepped. Application of sure wireless sensor is a most challenging work that can be convenient for the development of the electronic field as well as the telecommunication of broadcast use, it also has the ability of the size which is smaller, strength is low, cost-efficiently Figure 1 Wireless sensor nodes in FPGA based

Sensor and so on for the consider designed system. Due to the various kinds of these networks, the application of this algorithm must be suggested for their inter overbuilding attacks are shown in figure1. Some of the burdens can be contributed by the conformed assets in the energy, which can be activated by the logic gates which can be achieved from the hardware; the excellent storage capacity a present encrypted the information techniques in the purpose of size reduction by the encrypted algorithm. In the wireless channel have the tremendous to reduce the noise due to some interference and also fluctuations occur in the environment. That problem can be satisfied by the encryption algorithm on the output sides. In the standard algorithm, there are some challenges that can occur due to the process of Decryption, at the segment we use the initially determine records. Data encryption and the standard encrypted algorithm that can be used for security which occurs from the obstacles. The simulation of the bits can contain some challenge due to the process of Decryption that makes the one bit prior for the Decryption. These are considering as the significant problem in the future research works that make a profound impact on the wireless sensor application. There are two ways to solve the strategy in the request; one is doing the valid coding and mechanism property form the physical layer, it can help to improve the accuracy level and decreased the problem in the channel. Another one is to create a new approach for the introduction and investigating algorithm is used to encrypt that can be used to reduce the error propagation on this method.

Figure 2 Block diagram for sensor node based FPGA

From the figure 2 the sensor board send to the field programmable based gate array, it required the function after the manufacture the electronic circuits it passes on through the microcontroller is used to store the data information it also passes on through the wireless node and is would find the device function.

II RELATED WORKS

The design and implementation of MMf2 encryption are used to face the important challenge that can be faced from computer engineering. Which means that storage capacity. In modern architecture is depends on the reduced capacity and also used to reduce the size by the MMF2 encryption technique  (Nasrollahpour et al. 2018). The MMF2 is more advanced; it should be considered as the MMF2+ is used for the ferrofluids. In general, MMF2 is used for the testing method for the ferrofluids interior magnetic susceptibility and also valid for the wide range of concentration (Solovyova and Elfimova 2020). This work the MMF2 is used to get gain from the power quality devices through the signal. It also used to analyze and reduce the noise it should be considered as noise reduction. Next, it also increases the transient requirement of these signal and again the reduce the noise occur from the transient(Shadpey 2019).These methodology filters are merged the EMD they implement the adaptive signal processing dependent through the adaptive signal. Here the modified MMF2 is used to reduce the noise and is also implementing on the real-time development. (Prakash, et al. 2020).this model implement based on the switched reluctance machine on the FPGA based .they use another parameter lumped element modelling test it on experiment due to accuracy and RT applicable. It also controlled the situation(Fleming and Edrington, 2016).In this proposed work the implementation of Data encryption standard is used to encrypt the data information to get the excellent goal on the design by using less time consumer, high frequency, minimum low pulse for various kinds of Parameter such as high delay, setup time, hold time, skew path and so on(Thind et al. 2018). High performance of field-programmable gate array for the parallel process by the parallel processing element it should be considered as the virtual processor. They can be implemented from the fast compare to other processor and give the precise output from the processor(Zeebaree et al. 2019). The data information can be secure by the various kinds that can be essential to manage them its confidentiality from the concept we need the device to manage the secure the data information due to the data encryption standard algorithm to apply to the chip here the comparison depends on the 16 and 8 round function through efficiency(Kristianti et al. 2018).  The proposed work depends on the combination and determines the well known Field programmable gate array to implement the data encryption algorithm to secure the smart cards. That can be occupied by the smart card, size reduction chip area. Low power consumption with such restrictions on the area and power consumption and low throughput.(Dichou, et al. 2015). In this paper to secure, high performance, throughput level and sufficient area in FPGA implement on the data encryption algorithm they also successfully get the pipeline concept with the variable permutations (Swierczynski et al. 2015). Design and implementation of size reduction cypher blocks have been more favourable for the future purposes of cipher blocks in the unique specify system in the commonly consumed that can be valuable. In the certain, many size reduction cipher blocks have to be processed, by the recent utilization Advance encryption standard is considered as the commonly used algorithm in the FPGA implementation is endorsed for the security purpose in the electronic application, this algorithm can be reconstructed by the

Pervious information. The data encryption standard can do it with much secure level(Abdelwahab 2015). This algorithm can be implemented with the help of the logic gate, especially the use of the EX-OR function. It is well known because it is designed flexible at a regular period of them(Liu et al. 2013). In this paper implementation due to fault method and the theme of the various faults affects. By the purpose of using the various in deferential uniformity of S-boxes. These works depending on the improved, and optimized fault determine implementation by established, they are two types of differential, that can be considered due to the input and outputs differential. It also considers the relationship of both of them to finding the security(Yao and Kang 2011). In this paper implementation due to fault method and the theme of the various faults affects. By the purpose of using the various in deferential uniformity of S-boxes. This works depending on the improved, and optimized fault determine implementation by established, they are two types of differential, that can be considered due to the input and outputs differential. It also considers the relationship of both of them to finding the security level key(Al Azad 2012). In this paper, the propose of cypher block techniques that can be considered as the modified MMF2 is very acceptable for the embedded application for the linear as well as a non-linear differential algorithm. Here we use the 64 bits consider as the length of the blocks and size of the key it should be 80 bits. They include the nine repetitions for the round function.(Sauvage, et al. 2009). The commonly used structure can be optimized due to the cypher Feistel. In the important consideration known as Type2, and separate the information by constant > 2. The various blocks are arranged due to the Feistel formation for every block in the interior portion and also functioning the cycling transfer with the help of constant block. It has less diffusion and contains a large constant. That can be a not possible differential attack with the round function(Taherkhani et al. 2010). The main implementation in the design is processed against the power-dependent finder it can be investigated and improve this work from the method here we used the dummy S boxes to the less power consumption by using the general logic gates it could be constant, and if it random the same difficulties will occur less storage compared to existing method(Yang et al. 2011).

INTRODUCTION ON MMF2 IN FPGA

A mathematical requirement for the performance of the encrypted data information is made to be an algorithm. It is the chipper text, and it requires the purpose of the key to aligning the data information back into its original concept. The function of modified MMF2 techniques is attained from the round service with the Feistel designed structure due to the more number of input data bits, and the role of encryption can be shown in the figure 3and 4.Then we determine the follow of the round function designed to implement and structures by the determination and the created by the diffusion functionality.

Figure 3 Block diagram for encryption and Decryption

Figure 4 Encryption and Decryption

IMPLEMENTATION OF MMF2 ALGORITHM

The modified size-reduction blocks method are structured from the symmetric key algorithm for the encryption with the fixed dimension text that can be encrypted with the same dimension of size. The present works have 64 numbers of bits which contain the length of the block, and it includes 128 names of key bits including nine repetitions. The superior design of this method is Feistel network that can be utilizing the commonly used Type2 for its round operation. The bits have the remote key, and also it generates the key this process can be complicated that can represent the higher security level of the algorithm are shown in figure 5.

Figure 5 essential development schematic

The algorithm is selectively for decreased storage capacity and also has hardware memory. One of the challenges in the previous technique for the network application by using the four*four S box, the four*four boxes are less secure than the 8*8 box. But we use the proposed algorithm tom improve the security level of 4*4 from the differential and linear problem that can be protected. The design reduces the usage of repeated blocks from figure 6.

Figure 6 MMF2 algorithm structure

The function of F and Mk fixed are helping to contribute and improve the key in sub-block are shown in figure 7.

Figure 7 SDS in F function

There are 11 key series can be used in this method. The begin and end block in the design is considered as K0-K10; the other keys are considered as the nine keys for the round function. MK0-MK7 ranges can be determined by the use of 128 bits in the initial, the CK fixed. Both CK and 128 bits can be represented as,

CK=0x6db4acc9e21c820ff8b1d5ef5de2b0

The SDS block can be implemented to form by the purpose of F round function are shown in figure 8.

Figure 8 Structure of MMF2 recommended architecture.

Figure 9 Logic locking

When the input data can be protected from the circuits with the help of key inputs as well as tamper-proof memory in the system are shown in figure 9.

XOR logic gate is the exclusive digital gate that gives true when it is one, and it should be odd function here we use two input parameter x1 is a function with inventor is get the output y1and x2 are functioned it receives the output y2 are shown in the figure10.

Figure 10 XOR-based logic locking

The same process can be done in multiplexing operation are shown in figure 11. The binary 1s and 0s multiplication of digital output can be processed on the computer.

Figure 11 MUX based logic locking

STRUCTURE OF MODIFIED DES ALGORITHM

In this algorithm, everyone information can be separated by the frame; the condition of the channel are contributed as constant. When the frame, similar encrypted size of the block. So each frame-blocks are encrypted in multilevel. And the range of encryption size of blocks can be measured as well as optimized are shown the figure 12.

Figure 12 Modified DES block diagram

DES implementation of the cipher used the 16 round function structure. The 64 bits of block size and also find the length of the 64 bits; data encryption standard contains the well-known range of about 56 bits. Hence 8 of 64 bits of the key cannot be encrypted. The general data encryption method is depicted in the

Following are shown in figure 13.

Figure 13 Flow chart for modified DES implementation

KEY GENERATION ON DES

In the critical generation method on DES contains two various steps, the first step is to remove the check-in parity bits in the number of bit key (64 bits). The eight bits can be represented as parity checking, and it also removed the number of bits (56 bits). There are 48 bits looks different subkeys can be generated for each one of my 16 round functions on the data encryption standard.

They determine the first key by the separation of 56 bits into two data considered as 28 bit. Twenty-eight bits are contributed to the length of the data. Then both 28 bits are shifted left by either single or double bits based on the number of the round. The next step simply depends on the implementation of the resulting 48 bits permutation is shown in the figure14

.

Figure 14 Key generation on modified DES

RESULTS AND DISCUSSION

The simulation result depends on the clk= 1, rst= 0 there is no chip can be selected, and the generating key in [64:1] are shown in the figure15.

Figure 15 schematic sequential circuit of MMF2 with 64:1 key

. At the initial stage, it is considered as the initial process of the data is as follows. Despite the characteristic of the precious resource of the register in the internal within FPGA, plain text 64:1 This schematic model is shown below figure 16

Figure 16 RTL schematic

The simulation result of DES with the initial permutation IP with the round function is shown in number 17

Figure 17 simulation of the round function

The simulation result of DES with the round service in the round 1:2 are shown in figure 18

Figure 18 Simulation of round function round 1:2

The Parameter can be used in the simulation process and also find clock buffer and input/output buffer that can be shown in the below figure19.

Figure 19 Parameter used in DES

The parameters are used in the DES implementations are shown in table 1.

Table 1 Simulation parameters for proposed work

The proposed frequency 177.841 MHz are shown in the below figure15

Figure 15 Frequency response

To find the delay in the proposed fast median filter and also see the input/output delay in nanoseconds. There are destination ports 960 with the total number of paths 10040 occurs on it are shown in figure 16

Figure 16 Delay

Table 2 comparison Table

The above table 2 represents the comparison between the current and the proposed algorithm with the different Parameter such as frequency response, algorithm selection and delay.

CONCLUSION

In this paper, a modified data encryption standard algorithm, it can depend on the 16 round F function. We describe the encryption for the number of blocks, and the number of critical lengths can be increased. They also determine the security of its strength in the wireless sensor networks. This algorithm is used to reduce the delay when compared to the existing algorithm delay 5.62ns by using Data encryption standard (DES) algorithm.

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