ELEVATING THE PERFORMANCE OF MULTIPLE LEVEL RRAM-BASED MULTIPLEXERS VIA FPGA ARCHITECTURE

ELEVATING THE PERFORMANCE OF MULTIPLE LEVEL RRAM-BASED

MULTIPLEXERS VIA FPGA ARCHITECTURE

ABSTRACT

Resistive Random Access Memory (RRAM) is the unique technology used in CMOS Technology. The RRAM based multiplexers performs at high performance and low power consumption to routing the multiplexers. The existing architecture followed the way of one level multiplexer based FPGA to be organized by using 2T1R (2Transistor 1Resistor). In this paper the multi level multiplexer by using FPGA optimizations like Switch blocks are employed as a large multiplexer. The routing tracks are interconnected with Look Up Table (LUT) via cross bars. The total improvement of the multi level multiplexer RRAM based FPGA architecture can achieve the reduced area, channel width and power overhead problem, channel width performance more than the one level of multiplexer. The applications of the implemented system which includes Communication System to carry out the process of data transmission.

Keywords: RRAM, FPGA Architecture, Multiplexers, Routing Methodology

1. INTRODUCTION

            In recent years the promises have been made to the high-performance research efforts in the research of high performance RRAM FPGA, (Bazzi, Harb, Aziza, Moreau, & Kassem, 2020), (Njiki, Elouardi, Bouaziz, Casula, & Roy, 2019) to replace Static Random Access Memory (SRAM) by multiplexing based multinet architectures. RRAMs are not only used by a RRAM-based routing element to store multiplexer tree configuration but to route the data path  signals by means of a memory elements. As multiplexers based on RRAM can approach lower on-state resistors than SRAM multiplexers, they are of necessity more time efficient and lead to high-performance FPGA (Li & Shiau, 2019) architectures. It has been noted, in the contrast between RRAM-based FPGAs and SRAM-based implementation can be a 7%-15% gains in region, a 45% -58% reduction and 20%–58%energy (Tang, Giacomin, De Micheli, & Gaillardon, 2018). Nevertheless, earlier works typically employ 2T(Transistor)1R(RAM)-based circuit designs and focus only on the architectural impact of this technology. Minimal works examine realistic RRAM design restrictions, although they have a strong influence on the final performances of the architectures. However, in this paper we will see that the delay of RRAM-based multiplexers is independent of the size of the input and thus the architectural design space can be extended beyond the limitations of SRAM-based multiplexer (Tang, Giacomin, De Micheli, & Gaillardon, 2016). However, the RRAM-based multiplexer properties (Shirinzadeh & Drechsler, 2020) enable the FPGA architect to scale its routing multiplexers differently  by: privileging as much as possible multiple-level crossbars, made of large multiplexers. This paradigm shift in the topology of interconnections also requires rethinking the optimal architectural parameters which have been well determined for classical SRAM-based architectures. It is therefore worth finding properly-sized RRAM-based FPGA designs that can maximize the full potential of RRAM-based multiplexers and define the optimum design parameters correlated with them (Khaleghi & Asadi, 2018). The main contribution of the paper are Based on the current state-of-the-art structure, we investigate the circuit design aspects of RRAM based multilevel multiplexers. Through implementing circuit level enhancements, multi level multiplexers will achieve up to minimum delay in standard multiplexer routing. The new RRAM-based FPGA incorporates RRAM technology and design improvements to minimize Area-Delay (AD) then Power (PDP) relative to a traditional architecture-based SRAM-based FPGA.

The paper can be  organized in the form of Section 2 reviews the background of SRAM-based and previous works on RRAM-based FPGA architectures. Section 3 introduces the suggested methodology used in this paper. Section 4 presents the RRAM-based multiplexer design structure.  Section 5 shows the overall performance of the suggested architecture. Section 6 concludes the paper..

1. II. BACKGROUND

            In this section, we will first examine the well-optimized FPGA architectures based on SRAM, as well as previous research on FPGA architectures based on RRAM.

RRAM BASED FPGA       

            FPGAs are prefabricated reconfigurable machines that can be configured to incorporate various digital structures (Zambelli, Castellari, Olivo, & Bertozzi, 2018). By simply loading the target bitstream and reconfiguring the FPGA RRAM configuration bits (Arumí, Gonzalez, & Campabadal, 2017), divided into logic and routing fabrics, the flexibility of implementing versatile applications is facilitated. It is the responsibility of the logic blocks to implement the application functionality, while the routing resources provide the communication between logic blocks. The arrangement of logic and routing network determines the topology of the FPGA and hence the overall effectiveness of the FPGA was illustrated (Palchaudhuri & Dhar, 2019).

RRAM Technology

            RRAM employ a three layer structure, formed by a Top Electrode (TE), Bottom Electrode (BE), Switching metal oxide RRAMs switching mechanisms can be grouped into Unipolar Resistive Switching (URS) and Bipolar Resistive Switching (BRS) (Bersuker, Gilmer, & Veksler, 2019). Bipolar RRAMs are   considered in this paper, by following the choices of most RRAM-based parameters depicts the equivalent RC model of a RRAM. By providing the right combination of programming voltage and current, RRAMs can be freely switched between two stable resistance states: a High Resistance State (HRS) and a Low Resistance State (LRS) (Luo et al., 2020). A change in conductivity of a RRAM actually results the conductive filament in the switching layer, induced by a positive/negative programming voltage between TE and BE. The width of the filaments, which determines the LRS resistance, is strongly correlated to the programming current flowing through the RRAM. (Carboni & Ielmini, 2020) RRAMs are compatible with Back-End-of-Line process, and can be fabricated on the top of transistors at low cost. The filamentary conduction property brings to RRAMs not follows device-to-device variation but also follows the cycle-to-cycle variability. Both device-to-device and cycle-to-cycle variations are enabled to be well controlled. To be more robust in cycle-to-cycle variations, we can introduce program-verification strategy in programming RRAMs, similar to that of Flash memory. The inputs are inverted into two inverter and the outputs are given to the Look Up Table(LUT) (Xie, Cai, Wang, & Yang, 2020) and the output applied to the OR Gate operation to perform the  OR operation, its output is given to the Flip Flop and the OR output and the flip flop output given to the Multiplexer. The clock signal of OR output is depend upon the clock signal applied. The Multiplexer output reduced to one output to perform (2:1) operation (Cai et al., 2019). The Bit line and the word line operate to a CMOS technology. This method organizes the input and output to a speed and time evaluating whether the operation is delay or loss. Due to this, the bit streams of the CMOS technology implements to the both HRS and LRS.

III PROPOSED METHODOLOGY

In this system, we use the multilevel of multiplexers to enable the high performance level at a saturated level of activity. But now we detached the inverter by the way of direct connection to the Multiplexer.

Figure.1 Schematic representation of RRAM without buffers

Figure 1 represents the schematic representation of RRAM using without buffers.

1.Multi level RRAM based FPGA architecture:

Figure 2 RRAM design   without buffers

Figure 2 represents the implementation of RRAM design without buffers. The proposed routing architecture requires redefining the best fraction of routing tracks can be reached by each CB multiplexer. Note that in the classical architecture speed of 750 ns, all the nets mapped to the inputs of a CLB are different because the local routing can connect a net from a CLB input to multiple LUTs. The proposed architecture may have a net mapped to multiple CLB inputs due to the absence of local routing. Therefore, we need to increase Fc;in to allow more CLB inputs to be reached by a single routing track, to compensate the potential loss in routability.

In an FPGA tile, all the LUT inputs are connected to the right and bottom sides of a CLB. Each LUT has K=2 input connected to the right/bottom side of a CLB.

Figure 3 2T1R representation

Figure 3 in which the bit line and the write line have the alternate pulses like bit line is 0; the write line is 1. If the bit line is 1; the write line is 0 and vice versa. Both of them have the connection through by using 2T1R.  2Transistors 1Resitor (2T1R) operates at a certain input signals to regulates the average power consumption, maximum power and minimum power. 2T1R voltage source applied the CMOS module across the resistance, it acts like resistive component

.

2. 4T1R (4Transistor 1Resistor)

4T1R-based multiplexer only consists of the programming structures and input inverters of a first multiplexer and the output inverter of another multiplexer in a regular well. The output inverter and the associated programming structures will be located in a deep N-well, as well as the input inverters and associated programming structures of the other multiplexer. The transistor size here will be w/l=250 nm/140nm

Figure 4 4T1R representation

Figure 4. shows that the space required by the design rule between the regular well and the deep N-well can be  used to accommodate standard n-type transistors and route the multiplexers with the input signals. It imaginate the layout organization of the 16-input 4T1R based one-level multiplexer. The time period clock cycle variations- on and off between 200ns

3. 4Transistor 1Resistor to n level Structure

Figure 5 4T1R with n level Structure

Figure 5 represents the n level structure of 4T1R. In this structure, 4Transistors and 1 Resistor used to perform the high resolution output at n level of methods. This can acts as a resistive component with a readily integrated LUT, TE, BE through the designation of the feedback circuits. It always enhanced the scalability clock signals for some kind of feedback. The cumulative transistors are act like a resistive RAM through the n number of inputs at only using of 4 Transistors and 1 Resistor.

4. n level to 1 Multiplexer structure

Figure 6 Schematic Diagram of n level to 1 multiplexer

Figure 6 represents the schematic diagram of n level to 1 level multiplexer. This n level to 1 system clarifies the n number of inputs to enhanced to produce the only one output at a addition of  n number of  inputs to be supplied.

IV RESULT AND DISCUSSION

The output of the suggested method was represented in the waveform.

Waveform Output

To ensure that different Figure9, 10 LUT inputs can be connected from a common routing track, Fc;in should be at least 2=K. It depicts such an example when K = 6. Input in0 of LUT0 and input in0 of LUT1 can be reached by the same track Track0. Note that there is no need to allow two inputs of the same LUT to share a routing track. The case where two inputs of a LUT share  the same net can never happen because the inputs of a LUT are naturally logic equivalent. output voltage level was 0.8 v.

Figure 7 4T1R-based multiplexer output waveform

Figure 7 represents the output waveform of 4T1R.The input inverters are placed together in two stages so we can access to the multiplexer inputs from both sides through the horizontal lines (8 inputs in each side). The programming structures are placed above and under the input inverters and each associated Bit Line and Word Line are accessible through the vertical metal lines. As a result, the 4T1R-based multiplexer are is 1:4 which is more efficient than its CMOS counterpart.

In the performance analysis provides the operation function of existing and proposed method of RRAM based architecture. The applied input and its output of the given multi level designs are to be better than the existing method of by using RRAM based FPGA architecture. The output is followed below for the 4T1R, without buffers.

Figure8 Proposed output waveform

To evaluate the performance, low power and delay the method discussed in this study using novel  technology. All simulations are carried out using in a simulation tool at nominal conditions with proper frequency range. The transient analysis of Proposed Low Power and Delay for 4T1R can be represented below,

Figure 9 Proposed Output for without Buffers

Figure 8 and 9  shows the output waveform to perform the estimated output through the some advanced level of architectural methods at some propagated clock signals to the attained multiple level of input to the one output. The time taken through the whole process of one complete circle takes as 27 nano ohm. The bit line and the word line takes to the speed of very less of time at a some reduction of area, power consumption level for the RRAM process. For regular n level RRAM based FPGA architecture compared to one level RRAM based FPGA architecture less area occupy and have some same kind of activities to be performed, but n level multiplexer have more advantages than the one level of multiplexer.

The existing method output is followed by using the output waveform and its with buffers output waveform for the given input signals at a certain voltage source to be applied, it operates the 2:1 multiplexer operation of the given clock signal and the given feedback circuit. It attained the level of whole system as one level of working method.

Figure10 Existing Output waveform

Figure11 Existing output with Buffers

Figure10 and 11 shows the existing system waveform of overall output with buffers.

Table. 1 Implemented system output

Table.1 in which the overall performance of the entire process show to accomplish the demerits of one level RRAM based multiplexers to satisfy the multi level RRAM based multiplexer using FPGA architecture. The performance analysis should follow the redefined fraction numbers of given inputs and functionate the  various operations to satisfied the improved method. The above table given the total improvement of existing method through the operation of the multiplexer. The overall performance of the multi level RRAM based FPGA architecture declares minimum amount of performance at a time of highest area reduction, channel width, power overhead problem are reduced as compared to using instead of one level RRAM based FPGA architecture. This method enables the routing track via the baselines through the routability algorithms by the applied voltage source as same at all circuits. The baselines are lower than the routing tracks methodology.

Figure 12 Output waveform  of 4T1R to n level

Figure 12 represents 4T1R of n level waveform. As shown in figure 12 due to this stage, it performs the various operations and some operation. When supply voltage is applied to the input path of the multiplexer it converts it into the digital signals. The digital signals are executed the output to invert the signals at some clock signal to the feedback input of the given LUT.

 Figure13 Output waveform n level to 1 multiplexer  

Figure 13 shows the n level to 1 multiplexer output waveform.  It converts the given message to transform and to apply it for the next stage of OR Operation. It performs normal operation like input high means the output also high((1); or else the output is low(0). The output of the OR gate gives to the flip flop and the clock signals are given to the multiplexer box and finally the multiplexed data is to be connected to the NOT Gate. It generated the only one output at a high performed output. The Look Up Table performs the operation, whatever it we given the message transformed into the logic values in terms of 1 and 0 (high and low).The process continuously running because the output of the multiplexer is given to the input of the inverter. It performs like a feedback circuit.

The performance of the low power Delay is evaluated by comparing the average power, delay and power delay product. In general, a power delay product based comparison is appropriate for low power portable systems in which the battery life is the primary index of energy efficiency.

Table. 2 comparative analysis

From the table 2 it will be reveal that the proposed architectural enhancements can further improve area by 13.4%, delay by 9.2% and channel width by 11.25%. By implementing the architectural  enhancements, the proposed 4T1R can yiels Area-Delay Product by 50% and Delay-Power Product by 32.56%, as compared to a

classical architecture

1. CONCLUSION

In this paper, we characterized the topic of RRAM based FPGA architecture. RRAM based FPGA architecture exploits the scalability efficiency through 4T1R through the routing tracks via cross bar via Look up Table (LUT) and routing tracks Methodology with the Multiplexer with the application of number of Transistor and Resistor . For the existing system, the performance of RRAM based one level multiplexer identified the delay scales, power consumption, area occupy and various kinds of parameters are to be monitored. This made the quite delimits. In Proposed system, the above parameters are to be more efficient and high efficiency of the whole FPGA architecture attained the multi level multiplexer to overcome the performance instead of using one level RRAM multiplexer. RRAM based proposed system; the routability is lower than their applied voltage and time baselines due to the absence of local routing. This method mainly reduced the channel width and the reduced area compared to the one level RRAM based FPGA architecture.  The total

improvement of the Area-Delay Product (ADP) and Delay-Power Product (DPP) can be acquired by using multi level RRAM based FPGA architecture.

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