HIGH PERFORMANCE OF MULTIPLE LEVEL OF RRAM-BASED MULTIPLEXERS BY USING FPGA ARCHITECTURE

HIGH PERFORMANCE OF MULTIPLE LEVEL OF RRAM-BASED

MULTIPLEXERS BY USING FPGA ARCHITECTURE

 

 

Abstract

Resistive Random Access Memory (RRAM) is the unique technology used in CMOS Technology. RRAM performs at high performance and low power consumption to routing the multiplexers. The technique built one level of Multiplexer at a significant delay in its performance. The existing method, RRAM, followed the way of one level Multiplexer based FPGA architecture to be organized by using 2T1R (2Transistor 1Resistor). This scalability leads to affect the overhead problem with the delay overhead, power consumption, channel width of RRAM features. The RRAM regulate the Look-Up Table (LUT) by using routing tracks. LUT connected through via crossbar and Connection Block. In proposed system, we used the multi-level multiplexer by using FPGA optimizations like Switch blocks employ a large multiplexer. The routing tracks are interconnected with Look-Up Table (LUT) via crossbars. Length 4 is used instead of Length 2, 4T1R (4Transistor 1Resistor) used to reduced the area and also minimally sized programmable transistors. The total improvement of the multi-level multiplexer RRAM based FPGA architecture can achieve the reduced area, channel width and power overhead problem, channel width performance more than the one level of Multiplexer.

Keywords: RRAM, FPGA Architecture, Multiplexers, Routing Methodology

                 

1. INTRODUCTION

RRAM Technology has both high performance and low power to routing the multiplexers. Kyriakoulakos, Ket al. (2016) [1] stated the RAM could work the switching of HRS (High Resistance State) and LRS (Low Resistance State) modes. The benefits of RRAM are following: RRAM can reduce the resistance and capacitance leading the critical path. Once RRAM programmed, it does not affect the reduction of the operating voltage of the pass-transistors whose conductance degrade with reduction of Vdd. Tang, X. et al. (2017) [2] reviewed the RRAM based multiplexers had the high performance when the operating level reached as Vt. SRAM based Multiplexer has the insight properties of FPGA architecture like small crossbars at a multi-level of multiplexers like many to one formula. Tang, X. et al. (2016) [3] reported the RRAM based multiplexers to have the state-of-art like 4T1R (4 Transistor and 1 Resistor) to proposed delay improvements. The main advantages of 4T1R are the routing tracks are interconnected with Look-Up Table (LUT) via crossbars through instead of connection blocks and local routing. Burnett, D et al. (2014) [4] stated a novel FPGA architecture with RRAM programmable interconnects with the routing multiplexers. To identify the properly sized RRAM based FPGA architecture exploits high potential RRAM based multiplexers and obtained potential parameters. In this method, one level of crossbars providing large multiplexers through the HRS and LRS potential values..

Multiplexer based routing switches in FPGAs are implemented in tree structures with serial pass transistors for less SRAM-based storage of select bits. Dalgaty. T. et al. (2019) [5] stated the FPGA programmable interconnects usually contain three types of components: SRAM-based storage of configuration bits, Multiplexer based routing switches, and buffers. All three components are nontrivial parts in FPGAs, though CMOS-based programmable interconnects in FPGAs have been optimized, there are fundamental limitations in all three components of programmable. Each SRAM cell uses more than six transistors to store the one bit. Modern FPGAs enable serial bitstream programming by storing configuration bits in latch nodes embedded in a shift register structure, with an area overhead less than the SRAM-based memory storage. Also, these storage media are volatile; it causes excessive power consumption during standalone. Multiplexer based routing switches in FPGAs are implemented in tree structures with serial pass transistors for less SRAM-based storage of select bits. Each pass transistor has to be wide enough to provide sufficient drive, and this leads to a large footprint. In most cases, routing buffers in FPGAs exceed the buffering demand of a given application. The quantity and positions of routing buffers placed in each track of programmable interconnection are optimized to meet the worst-case of the track.

Problem Identification

In this part, the problem is to be identified by its working efficiency more than the existing method. The one-level multiplexer used to perform the 2T1R technique, it had the delimits of delay, reduced area, power overhead not yet highly performed.

Objective

• To propose the method of using without buffers performance.
• To propose the system of adding multi-level multiplexer to perform the enhanced routing tracks using 4T1R.
• To propose the area by less than 15%, delay by less than 10%, channel width by less than 13%.

Organization

The design methodology of RRAM based FPGA architecture and its effective function saw in section IV.

The performance Analysis is shown in Section V.

1. RELATED WORKS

As Non-Volatile Memory (NVM) based FPGAs gain increase the popularity. Yang, C. et al. (2019) [6] Reported the FPGA to synthesize the tools start to tune the synthesize the characteristics state-of-the-art NVM FPGA algorithms tried to reduce the high reconfiguration cost attained by the costly NVM programming process. However, they are not only limited in scalability but also failed to consider the process variation. Analog signals received by each transducer element are converted and coded on 12 bits. The data are stored on the FPGA chip memory. Njiki, M. et al. (2019) [7] Stated the first port is a write port used only to store acquisition data. These data are converted at 100 MHz, which needs a sampling period of 10 ns. Each memory bank is sufficient to store 8192 samples on each. Motivated by these potential performance gains, several programmable logic devices with different monolithically stacked configuration memory technologies have been reported through the flash memory.

Karakaya, B. et al. (2019) [8] Exhibited These memory technologies, required materials and processes that may not be compatible or scalable with CMOS processes. This presents the 3D-FPGA with added configuration memory based on the emerging non-volatile Resistive RAM, which is both compatible and scalable with CMOS technology. de Lima Kastensmidt, F. G. et al. (2014) [9] Reviewed the RRAM based FPGA architecture typically have the function of tile-based architecture, where high-density routing tracks interconnect an array of logic tiles. In each tile, there is a Configurable Logic Block (CLB), two Connection Blocks (CBs) and a Switch Block (SB). Routing tracks inside tiles are connected to CLB inputs by Connection Blocks, while Switch Blocks interconnected with the routing tracks between tiles. A CLB is composed of N Basic Logic Elements (BLEs) and a local routing architecture providing inner-block interconnections.

Kuon, I. et al. (2008) [10] Reviewed A BLE contains a factorable Look-Up Table (LUT), a Flip-Flop (FF) and a 2:1 multiplexer, which selects either a combinational or a sequential output. To improve the efficiency of arithmetic functions, commercial FPGAs widely enhance BLEs by adding more functionality, like adders and shift registers. Cong, J. et al. (2013) [11] Applied the purpose of accelerating arithmetic-intensive implementations; commercial FPGAs replace columns of tiles by Digital Signal Processor (DSP) and memory banks. Chatter, M. (1998) [12] Stated to implement a highly integrated synapse array device for matrix multiplication, a selector device with threshold switching and high ON-current characteristics is also required.

Moon.et al. (2019) [13] Reported the  FPGA-based platform is chosen to utilize its low investment cost, fast and easy system prototyping. Phadikar, A. et al. (2019) [14] Reviewed the design can be reconfigurable. The low-power hardware implementations of the lifting-based quality access control scheme of the grayscale image are not available in the literature to date. Liu, Y. F. et al. (2019) [15] Stated the presence of FPGA, expressive high-level synthesis tools; efficient CNN hardware designs still demand ingenious ways to optimize the use of available resources for achieving high-performance and low-power consumption.

Bielski, M. et al. (2019) [16] Stated the amount of image data grows, the computation of the algorithm that is implemented in FPGA becomes increasingly significant. Rao, P. S. et al. (2019) [17] Reported the traditional method of increasing the clock frequency is difficult to solve the system power consumption problem and the cache speed problem, reconfigurable hardware implementation of Field Programmable Gate Array (FPFA) low latency with high performance in real-time applications. Waidyasooriya, H. M. et al. (2019) [18] Stated the FPGA architecture provides the reprogram ability of application-specific solution while retaining we achieved up to 12.6 times speedup for single FPGA implementation and 23.8-time speed-up for two-FPGA application compared to a CPU. We also achieved over 9-times significant energy efficiency compared to a CPU-Based system.

Al-Aghbari, A. A. et al. (2019) [19] Based on the developed FPGA virtualization scheme, it allows users to create independent computing services on network-attached standalone FPGAs. Peltenburg, J. et al. (2019) [20] stated the interface of the virtual FPGA based CCM is automatically generated by a virtualization layer and based on the user’s specifications. An FPGA hypervisor has been developed that can be integrated with any cloud management tool.

III. PROBLEM STATEMENT

RRAM Technology

 RRAM employ a three-layer structure, formed by a Top Electrode (TE), Bottom Electrode (BE), Switching metal oxide RRAM switching mechanisms can be grouped into Unipolar Resistive Switching (URS) and Bipolar Resistive Switching (BRS). Bipolar RRAMs are considered in this paper, by following the choices of most RRAM-based parameters depicts the equivalent RC model of an RRAM. Besides the configurable resistance R, a parasitic capacitance CP induced by TE and BE shall also be considered. [3], By providing the right combination of programming voltage and current, RRAMs can be freely switched between two stable resistance states a High Resistance State (HRS) and a Low Resistance State (LRS). A change in conductivity of an RRAM results the conductive filament in the switching layer, induced by a positive/negative programming voltage between TE and BE. The width of the filaments, which determines the LRS resistance, is strongly correlated to the programming current flowing through the RRAM. RRAMs are compatible with Back-End-of-Line process and can be fabricated on the top of transistors at a low cost. The filamentary conduction property brings to RRAMs not follows device-to-device variation but also follows the cycle-to-cycle variability. Both device-to-device and cycle-to-cycle variations are enabled to be well controlled. To be more robust in cycle-to-cycle variations, we can introduce a program-verification strategy in programming RRAMs, similar to that of Flash memory. More details found in [3].RRAM have the 2R1R (2Transistor and 1 Resistor). The inputs are inverted into two inverters, and outputs are given to Look-Up Table(LUT) and output applied to OR Gate operation to perform  OR operation, its output is given to the Flip Flop, and the OR output and the flip flop output is given to the Multiplexer. The clock signal of OR output depends upon the clock signal applied. The Multiplexer output reduced to one output to perform (2:1) operation. The bit line and the word line operate to CMOS technology. This method organizes the input and output to speed and time evaluating whether the operation is delay or loss. Due to this, the bitstreams of the CMOS technology implements to both HRS and LRS.

 

 

 

1. SRAM based FPGA architecture:

     

SRAM based FPGA architecture is the early stage of structure to enhance the performance of the memory storage. The demand for more functionality and memory on the chip purpose for the continued scaling of SRAM devices. The 100Mb of SRAM thus requiring many advanced products use over the design of the cell and circuitry. To meet the voltage targets at the best yield and minimum levels. For example, SRAM cell needs to have more than 6.2 to achieve 95% yields on 128Mb of SRAM. In the SRAM device design with planner technologies the SRAM to provide stable cell operation at an optimized level. For FinFET technologies, the fins enable for the discrete nature quantized number, which in turn impacts the cell size directly. The substantial tradeoff in cell confirmation is increased with the size and increases the need for adequate robustness through the smallest cells. SRAM based FPGA architecture enabled on 4T1R (4 Transistor and 1 Resistor) process. To propagate the bit lines the switching linearity of the various activities through the bit line. In this methodology, it had the drawback of the reduced area by 7%, increase the performance by 45%, save the power consumption by 20%. We must attribute the participation of more reduced specification than the above SRAM based architecture. So we are proposed to RRAM based one level multiplexer for the high performance. This performed as two modes like Bit Line and Word Line. Fig.4 Both the switching modes act as an alternative input like as bit line input is 1 the word line is 0. If the bit line is 0, the word line is 1. Both are interconnected to make a disappear at a saturated level.

Fig.1 Structure of SSRAM

In Fig 1 represents the structure of SRAM, which is based on the structure of FPGAs, why long length wires, such as length-4 wires, are preferred is established on the fact that the delay of an SRAM multiplexer is larger than a long metal wire across a logic block.

 

1. One level RRAM based FPGA architecture

Resistive Random Access Memory (RRAM) is a promising non-volatile memory with the configurable method of data is to be stored. RRAM is to be configured at a resistance level of enhanced current and voltage characteristics of the linearity at some implementation process. In the early stages, SRAM used to analyze the performance of the channel width of the given input. SRAM based FPGA Architecture; high performance level do not require the changes.[2[, High level techniques are attractive than the architectural level because it needs to apply the implementation level. The high-level implementation technology is the use of redundancy, and the most well-known method is triple modular redundancy (TMR). FPGAs have a high logic density and for many applications. SRAM based FPGA is highly flexible because they are programmable, allowing the design changes and the program leads to a high logic density in terms of SRAM memory cells, several indefinite times can program SRAM cell. FPGA initializes all the SRAM bits on power-up and configures the bits with a user-supplied configuration.  In early level, SRAM can be used to store the memory through the analog circuits.

 

Fig.2 Flow diagram of RRAM with buffers

 

Fig.2 represents the flow diagram of RRAM with buffers. The one-level multiplexer to connected through the inverter input for the process of executing the Look Up Table (LUT) connected via crossbars of a small multiplexer. It will employ scalability of working through the clock signals of the OR Gate through via the multiplexer operation. It performs total output of (2:1) with the inverter operation. SRAM multiplexers naturally more delay-efficient and lead to high-performance architecture. Modern SRAM based FPGA architecture employs a tile-based architecture, where the tile-based array is interconnected with high-density routing tracks. In each tile, have CLB (Configurable Logic Block), CB(Connection Block), and SB(Switch Block). Routing track inside tile is connected with CLB (Configurable Logic Block) inputs by CBs. SRAM has the drawback of Area delay and Delay Power Product as compared to SRAM based FPGA architecture. To overcome the disadvantages of this, by using RRAM   based FPGA architecture.

 

 

Fig.3 Schematic diagram of one level RRAM  design with buffers

Fig 3 represents the schematic diagram of one level RRAM design. In RRAM based FPGA architecture, we should account the point of one level of Multiplexer to improve the delay, power consumption, area. In this method, when RRAM is programmed to LRS/HRS state, it propagates/blocks signals, similar to a transmission gate in on/off state. However, most RRAM-based researches overlook the challenges coming from physical designs, i.e., consider an ideal RRAM, which may lead to a strong bias in the estimation of any performance metric improvements. RRAM-based FPGAs can reduce the area by 15%, increase the performance by 58%, and save the power consumption by 58%, compared to one level of RRAM-based FPGAs. Very limited work studies the impact on novel RRAM-based FPGA architectures that exploit the circuit-level features of RRAM-based multiplexers. Fig.3 it is worthy of investigating specific architectural optimizations for RRAM-based FPGAs that would derive from realistic RRAM-based multiplexer designs. Now we proposed to RRAM derive the some kind of drawback in one level multiplexer using RRAM based FPGA architecture. In this RRAM based Multiplexer consist of three types like as Bit Line (BL), Word Line (WL), and Hold Mode (HM).

 

 

Fig.4 Schematic Diagram of 2T1R

Fig 4 represents the schematic diagram of 2T1R. The bit line and the write line have the alternate pulses like bit line is 0; the write line is 1. If the bit line is 1; the write line is 0 and vice versa. Both of them have a connection through by using 2T1R.  2Transistors 1Resitor (2T1R) operates at a specific input signal to regulates the average power consumption, maximum power and minimum power. 2T1R voltage source applied the CMOS module across the resistance; it acts like a resistive component. The output value as follows is by the same voltage source at a time of 0 to 1. The average power consumed is 7.35W. The maximum power 1.60W and minimum power are 6.75W.

Fig.5 Output waveform of 2T1R

Fig 5 showing the output waveform of 2T1R, which is used in one level RRAM architecture.

 

1. PROPOSED METHODOLOGY

Multi-level RRAM based FPGA architecture:

In this system, initially, we use the one level of RRAM based FPGA architecture. This contains the area reduction, power consumption, distortion through the system makes as disadvantages. The initial stage of multiple inputs given to the inverter. Now use the multilevel of multiplexers to enable the high-performance level at a saturated level of activity. But now we detached the inverter by way of direct connection to the Multiplexer.

Fig.6 Flow diagram of RRAM without buffers

Fig 6 represents the flow diagram of RRAM using without buffers.

Fig.7 Schematic diagram of RRAM design   without buffers

Fig 7 represents the schematic diagram of RRAM design without buffers. In proposed system consist of without buffer. The proposed routing architecture requires redefining each CB multiplexer can reach the best fraction of routing tracks. Note that in the classical architecture speed of 750 ns, all the nets mapped to the inputs of a CLB are different because the local routing can connect a net from a CLB input to multiple LUTs. The proposed architecture may have a net mapped to multiple CLB inputs due to the absence of local routing. Therefore, we need to increase Fc;in to allow more CLB inputs to be reached by a single routing track, to compensate for the potential loss in routability.

In an FPGA tile, all the LUT inputs are connected to the right and bottom sides of a CLB. Each LUT has K=2 input connected to the right/bottom side of a CLB. To ensure that different Fig.9, 10 LUT inputs can be connected from a typical routing track, Fc; in should be at least 2=K. It depicts such an example when K = 6. Input in0 of LUT0 and input in0 of LUT1 can be reached by the same track Track0. Note that there is no need to allow two inputs of the same LUT to share a routing track. The case where two inputs of a LUT share the same network can never happen because the inputs of a LUT are naturally logic equivalent. By considering architecture parameters K = 6, the proposed architecture requires Fc; in for the proposed architecture.

 

Schematic Diagram of 4T1R (4Transistor 1Resistor)

4T1R-based Multiplexer only consists of the programming structures and input inverters of a first multiplexer and the output inverter of another multiplexer in a conventional well. The output inverter and the associated programming structures will be located in a deep N-well, as well as the input inverters and associated programming structures of the other Multiplexer.

Fig.8 Schematic Diagram of 4T1R

 

Fig 8 displays the schematic diagram of 4T1R. The space required by the design rule between the conventional well and the deep N-well can be used to accommodate standard n-type transistors and route the multiplexers with the input signals. It imagines the layout organization of the 16-input 4T1R based one-level multiplexer.

 

Waveform Output

Fig.9 output waveform

Fig 9 represents the output waveform of 4T1R. The input inverters are placed together in two stages so we can access to the multiplexer inputs from both sides through the horizontal lines (8 inputs in each side). The programming structures are placed above and under the input inverters and each associated Bit Line and Word Line are accessible through the vertical metal lines. As a result, the 4T1R-based Multiplexer is 1:4_ more efficient than its CMOS counterpart.

 

1. PERFORMANCE ANALYSIS

In the performance, the analysis provides the operation function of the existing and proposed method of RRAM based architecture. The applied input and its output of the given multi-level designs are to be better than the existing method by using RRAM based FPGA architecture.

The proposed system output is followed below through the 4T1R, without buffers.

 

 

Fig.10 Proposed output waveform

Fig.11 Proposed Output for without Buffers

Fig 10 represents the proposed output waveform of the proposed model. Fig.11 shows the output waveform of without buffers to perform the estimated output through some advanced level of architectural methods at some propagated clock signals to the attained multiple level of input to the one output. The time taken through the whole process of one complete circle takes as 27 nano ohm. The bit line and the word line takes to the speed of very less of time at some reduction of area, power consumption level for the RRAM process. For regular n level, RRAM based FPGA architecture compared to one level RRAM based FPGA architecture less area occupy and have some same kind of activities to be performed, but n level multiplexer has more advantages than the one level of Multiplexer.

The existing method output is followed by using the output waveform and its with buffers output waveform for the given input signals at a specific voltage source to be applied; it operates the 2:1 multiplexer operation of the given clock signal and the given feedback circuit. It attained the level of the whole system as one level of the working method.

Fig.12 Existing Output waveform

Fig 12 and 13 shows the existing system waveform of overall output and with buffers.

Fig.13 Existing output with Buffers

 

Performance Comparison

Serial Number	Parameters	Existing       Method	Proposed Method
1	Power  overhead	20 Mega Ohm	27 Mega Ohm
2	Delay	10%	9.2%
3	Leakage Voltage	3V	2.7V
4	Area	15%	13.4%
5	Speed		51.25 ns
6	Channel width	13%	11.25%
7	Average Maximum Power	4.22	4.05
8	Average Minimum Power	1.1	0.16
9	Area-Delay Product	57%	50%
10	Delay-Power Product	38%	32.56%

Table. 1 Overall performance of the existing and proposed method

Table.1 The overall performance of the entire process show to accomplish the demerits of one level RRAM based multiplexers to satisfy the multi-level RRAM based Multiplexer using FPGA architecture. The performance analysis should follow the redefined fraction numbers of given inputs and functionate the  various operations to satisfied the improved method. The above table provided the total improvement of the existing method through the process of the Multiplexer. The overall performance of the multi-level RRAM based FPGA architecture declares the minimum amount of performance at a time of highest area reduction, channel width, power overhead problem are reduced as compared to using instead of one level RRAM based FPGA architecture. This method enables the routing track via the baselines through the routability algorithms by the applied voltage source as same at all circuits. The baselines are lower than the routing tracks methodology.

1. 4Transistor 1Resistor to n level Structure

Fig.14 4T1R with n level Structure

Fig 14 represents the n level structure of 4T1R. In this structure, 4Transistors and 1 Resistor used to perform the high-resolution output at n level of methods. Fig.15 acts as a resistive component with a readily integrated LUT, TE, BE through the designation of the feedback circuits. It always enhanced the scalability clock signals for some kind of feedback. The cumulative transistors act like a resistive RAM through the n number of inputs at only using 4 Transistors and 1 Resistor.

Fig.15 Output waveform  of 4T1R to n level

Fig 15 represents 4T1R of n level waveform.

1. n level to 1 Multiplexer structure

Fig.16 Schematic Diagram of n level to 1 multiplexer

Fig 16 represents the schematic diagram of n level to 1 level multiplexer.

This n level to 1 system clarifies the n number of inputs to enhanced to produce the only one output at addition of n number of  inputs to be supplied.  Fig 17 due to this stage, it performs the various operations and some operation. When the supply voltage is applied to the input path of the Multiplexer, it converts it into the digital signals. The digital signals are executed the output to invert the signals at some clock signal to the feedback input of the given LUT.

 

 Fig.17 Output waveform n level to 1 multiplexer    

Fig 17 shows the n level to 1 multiplexer output waveform.  It converts the given message to transform and to apply it for the next stage of OR Operation. It performs a normal operation like input high means the output also high((1); or else the output is low(0). The output of the OR gate gives to the flip flop, and the clock signals are given to the multiplexer box, and finally, the multiplexed data is to be connected to the NOT Gate. It generated the only one output at a high performed output. The Look Up Table shows the operation, whatever it we give the message transformed into the logic values in terms of 1 and 0 (high and low). The process continuously running because the output of the Multiplexer is given to the input of the inverter. It performs like a feedback circuit.

1. CONCLUSION

In this paper, we characterized the topic of RRAM based FPGA architecture. RRAM based FPGA architecture exploits the scalability efficiency through 4T1R through the routing tracks via cross bar via Look up Table (LUT) and routing tracks Methodology with the Multiplexer with the application of a number of Transistor and Resistor. For the existing system, the performance of RRAM based one level multiplexer identified the delay scales, power consumption, area occupy and various kinds of parameters are to be monitored. This made the quite delimits. In Proposed system, the above parameters are to be more efficient, and high efficiency of the whole FPGA architecture attained the multi-level multiplexer to overcome the performance instead of using one level RRAM multiplexer. RRAM based proposed system; the routability is lower than their applied voltage and time baselines due to the absence of local routing. This method mainly reduced the channel width and the reduced area compared to the one level RRAM based FPGA architecture.  The total improvement of the Area-Delay Product (ADP) and Delay-Power Product (DPP) by using multi-level RRAM based FPGA architecture.

 

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