CMOS FABRICATION

Introduction

An integrated circuit can be defined as a set of electronic circuits on a thin slice of semiconductor material such as silicon. An integrated circuit can comprise many microscopic components like transistors, capacitors, and resistors, which are connected to perform a given electronic task. Electronic devices such as computers on the early days were built using transistors and vacuum tubes. During that time, computers had limited capability and had a huge size. This required them to perform limited operation at a go, possess a huge cooling system due to overheating as well as consuming a lot of power. Two scientists made their first invention of the integrated circuits in 1959 [1]. One of the scientists from Texas, named Jack Kilby, invented and made his first integrated circuit made of germanium while the other, named Robert Noyce, made his first invention on the silicon-based integrated circuit the same year. This turned out to be one of the digital electronic breakthroughs. Before this time transistors were made one at a time and connected together manually. The planar manufacturing allowed many transistors to be built and connected simultaneously [2]. The invention by these scientists turned out to be the basic and the most prevailing invention in the digital electronic world, which is still used even up to date.

Figure 1: first integrated circuit [3].

The CMOS technology, standing for Complementary Metal Oxide Semiconductor, is a technology that is most popular in the manufacturing of integrated circuits in the microchip industry. There are different types of integrated circuits which include the analog integrated circuit, digital integrated circuit and the mixed-signal integrated circuit [4]. An analog integrated circuit is a type of an IC that functions by performing activities such as amplification, modulation, demodulation and filtering by tackling a continuous signal. A digital IC uses the binary process of “0” and “1” which contains millions of logic gates and flip flop in a single microchip. The mixed-signal integrated circuit comprises both digital and analog integrated circuit in a single microchip.

On building an integrated circuit, a semiconductor wafer such as silicon wafer is used as a working material whereby other electronic components such as transistors, resistors and capacitors are present in a reduced form to perform a specified task. Today integrated circuits are designed and built to accommodate many components such as transistors as predicted by Gordon Moore. He predicted that transistors would double every two years, and this is validated since today’s integrated circuits can accommodate billions of transistors [5]. Electronics today have increased their speed and performance. This has been made possible by technologies like CMOS technology which have made it possible for semiconductors industries. Today’s electronic devices like central processing units and phones are utilizing the CMOS technology which applies both the N-channel and the P-channel semiconductor components. To design and build the integrated circuits, we have to perform various manufacturing processes such as CMOS fabrication. The objective of this paper is to research various processes involved in CMOS fabrication [4]. CMOS fabrication can be made possible by using three different technologies which include the N-well and P-well technology, silicon on insulator and the twin well technology. While designing a complementary MOS circuit, three materials are fundamental-: they include semiconductors which are the base of the CMOS structure preferably silicon, the other materials are conductors used for conducting electricity and insulators, which are used to insulate the semiconductor and the devices. In CMOS fabrication (Figure 2), both the n-type and the p-type MOSFETs are designed and arranged in a way that the p-type will act as the pull up network while the n-type act as the pull-down network [6].

Figure 2: CMOS processing [7].

1.     Processes in CMOS Fabrication

1.1.           Oxidation

This is the process by which a silicon dioxide layer is produced on the surface of a silicon wafer by reacting silicon with oxygen (Figure3). This is achieved by heating the silicon wafer in what is known as an oxidizing condition in a process known as thermal oxidation. In order to fasten up this chemical reaction, the process must be performed at a high temperature of 1000-1200⁰C inside a very clean furnace in order to avoid any sort of contamination [8]. To achieve an ultraclean furnace particle filter are used, which ensures that the airflow in the furnace is dust-free. The oxygen used in the oxidation process can either be introduced as steam which is known as wet oxidation or as a high purity gas in a process known as dry oxidation. Wet oxidation process has a very high growth rate while the dry oxidation leads to better electrical properties. Silicon oxide has an approximate dielectric strength of 10⁷V/cm and a 3.9 dielectric constant, making it a suitable source for making MOS capacitors. Silicon dioxide also serves as a protective layer from impurities that only allow doping on silicon surfaces and not on one covered by the oxide [4]. A silicon surface is highly reflective, while the silicon oxide is transparent. This causes the reflection of certain colors when white light is directed on the oxide wafer.

Figure 3: oxidation in CMOS fabrication [9].

1.2.           Diffusion

Diffusion, as we all know, is the process of particles or atom movement from region f high concentration to region of low concentration. An example of a diffusion process is when a drop of ink disperses through a glass of water. Diffusion in relation to integrated circuits is one of the processes in very large scale integration (VLSI) fabrication which is the process of combination of billions of transistors into a single microchip. In very large scale integration (VLSI) fabrication, diffusion is a process of introducing impurity atoms into the silicon to change its resistance. The diffusion rate of atoms into silicon is a function of temperature, and it usually takes place at a temperature of about 1000⁰C to 1200⁰C to obtain the desired results [6]. The process of diffusion, in this case, takes place in a furnace similarly to those that are used in the oxidation process of silicon. The rate or depth at which atoms(impurities) diffuses depends upon the processing time and the temperature. In this process, the commonly used impurities are arsenic, phosphorous and boron. Both phosphorous and arsenic are n-type dopant, while boron is a p-type dopant [4]. A PN junction, commonly known as a diode, is formed when boron which is a p-type dopant is diffused into an n-type dopant. In some cases, these dopants are usually masked using a thin layer of silicon dioxide. A diffused layer can also be used as a conductor if the doping concentration is high because of its low resistivity.

1.3.           Ion implantation

Ion implantation is a process of accelerating impurity ions to high speed and physically introduced to crystal substrate to change its electrical property. In this process, the ions are vaporized and directed to silicon at high velocity. The dopant ions lodge into the crystal lattice then collide with the silicon atom loose energy and finally rest within the lattice. In this process the gases that has the target dopant is ionized at the ion source [10]. The penetration depth of ions is dependent on the energy of the ion beam which is controlled by using acceleration-field voltage. Therefore, one can control the ion quantity implantation by varying the current of the beam. This process results in a more accurate result than that of the diffusion process since voltage and current are easier to measure and control [8]. This process can take place at room temperature, and it is the most suitable process for doping.

1.4.           Deposition

In CMOS fabrication, deposition can be described as the process depositing different materials on a silicon wafer. Examples of materials deposited are: Aluminium, silicon nitride (Si₃N₄), polysilicon silicon dioxide and copper [2]. To perform this process one can use different methods which include:

• The sputter deposition method
• Low-pressure chemical vapor deposition
• Plasma-assisted chemical vapor deposition
• Chemical vapor deposition

1.5.           Etching

This is another process in CMOS fabrication where there is selective removal of material on the silicon wafer. While performing etching process there are factors that should be taken into consideration, they include:

• The etch selectivity: this involves etching of a selected material at a greater rate than the other materials.
• The etch anisotropy: it is fabrication process that is subtractive which aims in removal of certain materials in a given direction to attain a flat shape.

The etching process can be categorized into two different processes.

• Wet etching- this is the process of removing certain materials from a wafer using chemicals in liquid form.
• The dry etching- process of removing a semiconductor masked pattern by the method of ion bombardment.

1.6.           Epitaxy

This is the process of formation of silicon’s single crystal of the silicon material surface to ensure continuity of the crystal structure across the interface. It is difficult to deposit N on N+ silicon using diffusion process, therefore epitaxy is the best method to be used. this process is also used in isolating bipolar transistors where N is deposited on P. This process involves a sequence of operation that include:

2. Heating the silicon wafer to a temperature of 1200⁰C
3. Reduce SiO2 on the surface by turning H2 on
4. Remove contaminant and a small amount of silicon by turning on anhydrous hydrogen chloride.
5. Turn off the hydrogen chloride
6. Dropping he temperature to 1100⁰C
7. Turn on the silicon tetrachloride
8. Introduce the dopant

8.1.           Lithography

Lithography is a process used to record binary image on a photoresist layer spun over a semiconductor wafer. The photoresist layer is a photosensitive material which gets soluble on the exposure to the light [6]. Soft baking is used to prepare the silicon substrate on which the integrated circuit is designed and built on. The layout image that is formed by light into small images is resolved by lens, then they get reflected on the layer of the photoresist. Photoresist parts that are exposed to the light are rinsed away, leaving the unexposed zones on the silicon wafer. Then the silicon wafer is baked hard in order to set the remaining photoresist [10]. The multilayers on the surface such as silicon dioxide, silicon nitride and metal are removed by the process known as etching from the regions that are exposed whereby the remaining parts photoresist is removed.

8.2.           Metallization

Metallization process is the final step in CMOS fabrication. It can be defined as the process by which the integrated circuit components are integrated and connected using a conductor material such as aluminium. Metallization lead to the production of a metal layer that is a thin film which acts as the conductor pattern for integrated circuit components interconnection. This process also plays a major role in producing a metalized region for wire bonding from the microchip packaging. The wire used for bonding are approximately 25micrometer in diameter while the bonding pads are 10000 micro-meter square. Aluminium is the most commonly used material in metallization process of most integrated circuits and transistors. The reason why it is the most preferred metal is due to its good conductivity property, aluminum fil is easy to deposit by just using a vacuum evaporation, it also produces a suitable bonding with silicon by alloying and sintering at 577⁰C and 500⁰C respectively and also it produces a non-rectifying and low resistance connection with a p-type silicon. The metallization process can be classified into two categories. The first category is the chemical vapor deposition and the other is the physical vapor deposition.

9.     N- Well CMOS Technology

The regions of the n-well are formed for the p-type transistors by the process of the dopant implantation into the silicon wafer. This process has a lower substrate bias effect on the breakthrough and the threshold voltage [2]. The integrated circuit do not conduct electricity at a high voltage gate but conduct at a low voltage at the gate. Integrated circuits that are produced by the NMOS fabrication are faster than those built by the p-MOS fabrication because the electrons are the carriers which travel twice as fast as the holes.

10.                        P-Well CMOS Technology

In the p-well process, we use the n-type as the substrate whereby the devices are fabricated by diffusion and masking. The p-well is diffused in to the n-type substrate in order for the n-type electronic components to be accommodated [2]. A deeper diffusion process is required in this process because the voltage breakthrough and the threshold of the n-type transistor is affected by the concentration of the p-well.

11.                        Twin Tube process

Also referred to as Duel-well comprises of both the n-well and the p-well processes for the PMOS and the NMOS transistors are created on a similar silicon wafer. In this process, the threshold voltage and the trans conductance can be separately optimized [2]. The P+ wafer is the first material in this process with the epilayer. The twin tube process take place in various steps.

Figure 5: twin tube CMOS [9].

12.                        Deep Submicron (DSM) CMOS Fabrication Step by Step

1. First step: the starting silicon wafer must be doped so as to facilitate conductivity

Figure 6: first step of CMOS fabrication process [11].

2. P-well and the n-well: in this step, the PMOS and the NMOS transistors will be fabricated in the n-well and p-well respectively

Figure 7: The p-well and N-well diagram [11].

3. The third step is the isolation of the shallow Trench which isolates one transistor from the other electrically. This process purpose is to prevent the leakage of the electric current between adjacent semiconductor components.

Figure 8: isolation of the shallow trench CMOS fabrication step [11].

4. The forth step is the threshold shift and the Anti-punch through implantation. NMOS has a threshold of approximately 0V while the PMOS transistor has an approximately -1.2v. In this process the NMOS is usually made harder to invert while the PMOS easy in voltage threshold which is balanced at about 0 value using an implant.

Figure 9: fourth CMOS fabrication step- implantation of anti-punch and threshold shift [11].

5. Deposition of thin oxide which is followed by the polysilicon. Deposition of these layer is performed specifically on regions that are needed.

Figure 10: 5th step – thin oxide and polysilicon deposition [11].

6. In the six step a light-doped source and drain is formed using a light doped implant.

Figure 11: sixth step of light doping the source and drain [11].

7. In this step a layer of the dielectric gets deposited on the wafer surface and removed to produce a sidewall spacer which will be adjacent to the thin oxide polysilicon. This wall spacer play part in preventing doping of the source and drain.

Figure 12: seventh step-deposition of a layer of dielectric on silicon wafer [11].

8. A complete source and drain is formed in this process (ion implantation)

Figure 13: formation of a complete source and drain through ion implantation [11].

9. Polysiliciding and siliciding take place in this step which are used in reduction of the resistivity by introduction of a low resistance silicide, for instance TiSi2 and TaSi2 on the top of the diffusion. Siliciding is the process of introducing a silicide component a component that comprises of a silicon.

Figure 14: ninth CMOS fabrication step- siliciding and Polysiliciding to reduce resistivity [11].

10. In this step a layer of oxide is formed to enclose transistors as well as to planarize the wafer surface.

Figure 15:formation of a layer of oxide to cover transistors [11].

11. In this step, formation of the plugs known as tungsten take place through the lower oxide layer, which provides the connection between devices, the substrate and p-well and the N-well to the first level of the metal. This process is followed by the second level metal. After few metallization processes a final and completed fabrication is achieved.

Figure 16: A complete fabricated CMOS [11].

13.                        CMOS LOGIC GATES

A CMOS logic gate can be defined as a system which comprise of the NMOS pull-down network and the PMOS pull up network which are connected to an output “0” and output “1” respectively.  MOSFET transistors are used to build CMOS logic gates rather than the bipolar junction based transistors. The pulldown and pull up transistors are used in preventing the logic gates input from floating when it is driven by a single source which is capable of current sinking. In this section, the paper focus on different ways to build different types of Complementary logic gates. The CMOS microfabrication process comprises of a frontend step which involves doping profiles and diffusion. The gate poly deposition, etching, lithography and gate oxidation are involved in the gate module as well as the source and drain diffusion. In CMOS logic gates the front and back ends are separated using contacts. The PMOS transistors are designed in such a way that they consist of an input coming from the source of voltage or from other transistors while the CMOS gets its input from another transistor or the ground. A logic gate is built on a p-type substrate, the base layer comprises of the diffusion, the n-well and the polysilicon which are placed in the trench of the p-substrate. The contacts make the connection by penetrating through the insulating layer which is between the first layer of the meta and the base layer. For instance, the NAND inputs are in the polysilicon while the intersection of the diffusion and the polysilicon are used to form the transistors.

13.1.       CMOS Logic Gates Layout design rule.

As processes in VLSI design becomes more complex, the designers need to understand the complexity of the CMOS fabrication process and interpreting the relationship between various photo mask can be troublesome. Therefore, design rules have to be introduced to act as communicating link between the process engineer and the circuit designer during the process. These design rules help in achieving a circuit with optimum yields in a minimal area possible without interfering with the circuit reliability. Design rules arises because of manufacturing problem such as: tearing and photoresist shrinkage, The thickness of the oxide, temperature, material deposition variations, and impurities. These manufacturing problems may lead to transistor problems, for instance, variation in the threshold voltage which occur due to variation in poly layer, thickness of the oxide, and the ion implantation. In order to prevent and reduce these problems, the design rules specify certain geometric constrain on the circuit layout to the designers. These geometric constraints include the minimum spacing and minimum width.  Interaction between different layers and geometric reproduction of feature are the primary issue addressed by the design rule. There are two different types of design rule which include;

Absolute design rule – in this type of design rule, the design rules are expressed in absolute dimensions (μ-based). In this approach, scaling is more demanding and has to be done manually or sometime using CAD modelling tool.

Scalable CMOS layout design rule – All design rules are defined in terms of a single parameter lambda (λ) in this approach. This is because Lambda can be easily scaled in various fabrication processes as the technology advances.

13.2.       Building a NAND Gate

A CMOS NAND gate is formed by connecting the PMOS transistors in parallel and the NMOS transistors in series in vertical connection. The PMOS NAND gate act as a pull up network while the NMOS act as a pull down network [12].  In the truth table, if either of the input is low at least one of the pull up network will be ON while at least one of the NMOS transistor will be OFF therefore resulting to a high output. Is input A and B are high “1” all transistors in the NMOS NAND gate and PMOS NANG gate will be ON and OFF respectively.

Figure 18: CMOS NAND Gate [12]

13.3.       Building an Inverter Gate

An inverter gate is a logic gate that implements the negation logic. it consists of a single PMOS and a single NMOS transistor. The PMOS transistor ha sit input from the Vdd while the NMOS transistor has its input from the Vss (ground). An inverter gate layout composes of six different masks which include: n-well, polysilicon, diffusion, Diffusion, metal and contact. An inverter gate can be used in a NAND gate and NOR gate to form an AND gate and an OR gate respectively.

Figure 19: an inverter gate layout

13.4.       Building an AND Gate

An AND gate is built by connecting parallel connected PMOS NAND Gate with a serial connected NMOS NAND gate and adding and adding a CMOS inverter which invers the output signal. If at least one of the input is low “0”, it results to an output which is high “1” in a CMOS NAND gate therefor adding an inverter will result to an output which will be low in a CMOS AND gate [12]. If all inputs are high “1” the resulting output is low in a NAND gate but due to an inverter in an AND gate the output will be high “1”.

13.5.       Building a NOR Gate

CMOS NOR Gate is formed on connecting a PMOS NOR gate as the pull up network and the NMOS NOR gate as the pull down network. The PMOS transistors in the NOR gate are connected in series so as to pull up the output high when the two inputs are low while the NMOS transistors are in parallel so as to pull down the output to low when either of the input is high. A NOR gate is simply a digital logic which implements the logical NOR. A truth table of the logical NOR indicates that when all the inputs are low “0”, the output of the gate will be high “1”. A low “0” output is achieved when the inputs at the NOR gate are both high or one of them is high. The NOR logic gate is the negation of the OR gate and he the property of the ability to form other logic function [12].

Figure 21: CMOS NOR Gate [12].

13.6.       Building an OR Gate

The CMOS OR gate is built by using the basis of the NOR gate function and adding an inverter on the output. An OR gate is built by connecting the serial connected PMOS gate with a parallel connected NMOS gate and adding an inverter onto the output. The PMOS gate and the NMOS gate acts as the pull up and pull down networks respectively. If all the inputs are low “0”, the output of the NOR gate will be high “1” therefore the output of the OR gate will be low due to the inverter introduced on the output of the CMOS NOR gate. If both of the input or one of the input is high “1”, the output in a NOR gate will be low “0”, but in an CMOS OR gate the output will be high “1” due to the inverter.

Conclusion

Today electronic devices have become more powerful and small in size. For the last four decade semiconductors companies have thrived to ensure the growth and improvement of these electronic devices. To facilitate this, processes like the CMOS fabrication have facilitated in creation of an era of evolution and miniaturization in the electronic community. This is evident through the ever-growing fabrication of billions of transistors in integrated circuits. This research paper provide various processes involved in CMOS fabrication. The paper also helps in understanding more on what make up a CMOS fabrication technology. Also, different types of CMOS logic gates are discussed and how they are built.

References